lscpu - TEST07
Architektur: x86_64
CPU Operationsmodus: 32-bit, 64-bit
Adressgrößen: 39 bits physical, 48 bits virtual
Byte-Reihenfolge: Little Endian
CPU(s): 20
Liste der Online-CPU(s): 0-19
Anbieterkennung: GenuineIntel
Modellname: Intel(R) Core(TM) i9-10900 CPU @ 2.80GHz
Prozessorfamilie: 6
Modell: 165
Thread(s) pro Kern: 2
Kern(e) pro Socket: 10
Sockel: 1
Stepping: 5
Maximale Taktfrequenz der CPU: 5200,0000
Minimale Taktfrequenz der CPU: 800,0000
BogoMIPS: 5599.85
Markierungen: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp lm constant_tsc art arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc cpuid aperfmperf pni pclmulqdq dtes64 monitor ds_cpl vmx smx est tm2 ssse3 sdbg fma cx16 xtpr pdcm pcid sse4_1 sse4_2 x2apic movbe popcnt tsc_deadline_timer aes xsave avx f16c rdrand lahf_lm abm 3dnowprefetch cpuid_fault ssbd ibrs ibpb stibp ibrs_enhanced tpr_shadow flexpriority ept vpid ept_ad fsgsbase tsc_adjust bmi1 avx2 smep bmi2 erms invpcid mpx rdseed adx smap clflushopt intel_pt xsaveopt xsavec xgetbv1 xsaves dtherm ida arat pln pts hwp hwp_notify hwp_act_window hwp_epp vnmi pku ospke md_clear flush_l1d arch_capabilities
Virtualisierung: VT-x
L1d Cache: 320 KiB (10 instances)
L1i Cache: 320 KiB (10 instances)
L2 Cache: 2,5 MiB (10 instances)
L3 Cache: 20 MiB (1 instance)
NUMA-Knoten: 1
NUMA-Knoten0 CPU(s): 0-19
Schwachstelle Gather data sampling: Mitigation; Microcode
Schwachstelle Itlb multihit: KVM: Mitigation: VMX disabled
Schwachstelle L1tf: Not affected
Schwachstelle Mds: Not affected
Schwachstelle Meltdown: Not affected
Schwachstelle Mmio stale data: Mitigation; Clear CPU buffers; SMT vulnerable
Schwachstelle Retbleed: Mitigation; Enhanced IBRS
Schwachstelle Spec rstack overflow: Not affected
Schwachstelle Spec store bypass: Mitigation; Speculative Store Bypass disabled via prctl
Schwachstelle Spectre v1: Mitigation; usercopy/swapgs barriers and __user pointer sanitization
Schwachstelle Spectre v2: Mitigation; Enhanced / Automatic IBRS, IBPB conditional, RSB filling, PBRSB-eIBRS SW sequence
Schwachstelle Srbds: Mitigation; Microcode
Schwachstelle Tsx async abort: Not affected