reapplythermalpaste-offset01
AMD Ryzen 5 2600X Six-Core testing with a ASUS ROG STRIX B450-F GAMING (2008 BIOS) and Sapphire AMD Radeon RX 56/64 8GB on Arch rolling via the Phoronix Test Suite.
AMD Ryzen 5 2600X Six-Core
Processor: AMD Ryzen 5 2600X Six-Core @ 3.60GHz (6 Cores / 12 Threads), Motherboard: ASUS ROG STRIX B450-F GAMING (2008 BIOS), Chipset: AMD Family 17h, Memory: 16384MB, Disk: 240GB ADATA SX8200NP + 275GB Crucial_CT275MX3, Graphics: Sapphire AMD Radeon RX 56/64 8GB (1590/900MHz), Audio: AMD Vega 10 HDMI Audio, Monitor: IPS235 + Panasonic-TV, Network: Intel I211
OS: Arch rolling, Kernel: 5.0.8-arch1-1-ARCH (x86_64), Display Server: X Server 1.20.3, OpenGL: 4.5 Mesa 19.0.2 (LLVM 8.0.0), Compiler: GCC 8.3.0 + Clang 8.0.0 + LLVM 8.0.0, File-System: ext4, Screen Resolution: 2944x1280
Kernel Notes: amdgpu.ppfeaturemask=0xffffffff
Processor Notes: Scaling Governor: acpi-cpufreq schedutil
Security Notes: __user pointer sanitization + Full AMD retpoline IBPB: conditional STIBP: disabled RSB filling + SSB disabled via prctl and seccomp
Primesieve
Primesieve generates prime numbers using a highly optimized sieve of Eratosthenes implementation. Primesieve benchmarks the CPU's L1/L2 cache performance. Learn more via the OpenBenchmarking.org test page.
AMD Ryzen 5 2600X Six-Core
Processor: AMD Ryzen 5 2600X Six-Core @ 3.60GHz (6 Cores / 12 Threads), Motherboard: ASUS ROG STRIX B450-F GAMING (2008 BIOS), Chipset: AMD Family 17h, Memory: 16384MB, Disk: 240GB ADATA SX8200NP + 275GB Crucial_CT275MX3, Graphics: Sapphire AMD Radeon RX 56/64 8GB (1590/900MHz), Audio: AMD Vega 10 HDMI Audio, Monitor: IPS235 + Panasonic-TV, Network: Intel I211
OS: Arch rolling, Kernel: 5.0.8-arch1-1-ARCH (x86_64), Display Server: X Server 1.20.3, OpenGL: 4.5 Mesa 19.0.2 (LLVM 8.0.0), Compiler: GCC 8.3.0 + Clang 8.0.0 + LLVM 8.0.0, File-System: ext4, Screen Resolution: 2944x1280
Kernel Notes: amdgpu.ppfeaturemask=0xffffffff
Processor Notes: Scaling Governor: acpi-cpufreq schedutil
Security Notes: __user pointer sanitization + Full AMD retpoline IBPB: conditional STIBP: disabled RSB filling + SSB disabled via prctl and seccomp
Testing initiated at 22 April 2019 20:40 by user jasondaigo.