hwloc-ls - aom-av1-3.7.0-mllvm-disable-object-based-analysis
Machine (2267GB total)
Package L#0
NUMANode L#0 (P#0 1134GB)
L3 L#0 (32MB)
L2 L#0 (1024KB) + L1d L#0 (32KB) + L1i L#0 (32KB) + Core L#0 + PU L#0 (P#0)
L2 L#1 (1024KB) + L1d L#1 (32KB) + L1i L#1 (32KB) + Core L#1 + PU L#1 (P#1)
L2 L#2 (1024KB) + L1d L#2 (32KB) + L1i L#2 (32KB) + Core L#2 + PU L#2 (P#2)
L2 L#3 (1024KB) + L1d L#3 (32KB) + L1i L#3 (32KB) + Core L#3 + PU L#3 (P#3)
L2 L#4 (1024KB) + L1d L#4 (32KB) + L1i L#4 (32KB) + Core L#4 + PU L#4 (P#4)
L2 L#5 (1024KB) + L1d L#5 (32KB) + L1i L#5 (32KB) + Core L#5 + PU L#5 (P#5)
L2 L#6 (1024KB) + L1d L#6 (32KB) + L1i L#6 (32KB) + Core L#6 + PU L#6 (P#6)
L2 L#7 (1024KB) + L1d L#7 (32KB) + L1i L#7 (32KB) + Core L#7 + PU L#7 (P#7)
L3 L#1 (32MB)
L2 L#8 (1024KB) + L1d L#8 (32KB) + L1i L#8 (32KB) + Core L#8 + PU L#8 (P#8)
L2 L#9 (1024KB) + L1d L#9 (32KB) + L1i L#9 (32KB) + Core L#9 + PU L#9 (P#9)
L2 L#10 (1024KB) + L1d L#10 (32KB) + L1i L#10 (32KB) + Core L#10 + PU L#10 (P#10)
L2 L#11 (1024KB) + L1d L#11 (32KB) + L1i L#11 (32KB) + Core L#11 + PU L#11 (P#11)
L2 L#12 (1024KB) + L1d L#12 (32KB) + L1i L#12 (32KB) + Core L#12 + PU L#12 (P#12)
L2 L#13 (1024KB) + L1d L#13 (32KB) + L1i L#13 (32KB) + Core L#13 + PU L#13 (P#13)
L2 L#14 (1024KB) + L1d L#14 (32KB) + L1i L#14 (32KB) + Core L#14 + PU L#14 (P#14)
L2 L#15 (1024KB) + L1d L#15 (32KB) + L1i L#15 (32KB) + Core L#15 + PU L#15 (P#15)
L3 L#2 (32MB)
L2 L#16 (1024KB) + L1d L#16 (32KB) + L1i L#16 (32KB) + Core L#16 + PU L#16 (P#16)
L2 L#17 (1024KB) + L1d L#17 (32KB) + L1i L#17 (32KB) + Core L#17 + PU L#17 (P#17)
L2 L#18 (1024KB) + L1d L#18 (32KB) + L1i L#18 (32KB) + Core L#18 + PU L#18 (P#18)
L2 L#19 (1024KB) + L1d L#19 (32KB) + L1i L#19 (32KB) + Core L#19 + PU L#19 (P#19)
L2 L#20 (1024KB) + L1d L#20 (32KB) + L1i L#20 (32KB) + Core L#20 + PU L#20 (P#20)
L2 L#21 (1024KB) + L1d L#21 (32KB) + L1i L#21 (32KB) + Core L#21 + PU L#21 (P#21)
L2 L#22 (1024KB) + L1d L#22 (32KB) + L1i L#22 (32KB) + Core L#22 + PU L#22 (P#22)
L2 L#23 (1024KB) + L1d L#23 (32KB) + L1i L#23 (32KB) + Core L#23 + PU L#23 (P#23)
L3 L#3 (32MB)
L2 L#24 (1024KB) + L1d L#24 (32KB) + L1i L#24 (32KB) + Core L#24 + PU L#24 (P#24)
L2 L#25 (1024KB) + L1d L#25 (32KB) + L1i L#25 (32KB) + Core L#25 + PU L#25 (P#25)
L2 L#26 (1024KB) + L1d L#26 (32KB) + L1i L#26 (32KB) + Core L#26 + PU L#26 (P#26)
L2 L#27 (1024KB) + L1d L#27 (32KB) + L1i L#27 (32KB) + Core L#27 + PU L#27 (P#27)
L2 L#28 (1024KB) + L1d L#28 (32KB) + L1i L#28 (32KB) + Core L#28 + PU L#28 (P#28)
L2 L#29 (1024KB) + L1d L#29 (32KB) + L1i L#29 (32KB) + Core L#29 + PU L#29 (P#29)
L2 L#30 (1024KB) + L1d L#30 (32KB) + L1i L#30 (32KB) + Core L#30 + PU L#30 (P#30)
L2 L#31 (1024KB) + L1d L#31 (32KB) + L1i L#31 (32KB) + Core L#31 + PU L#31 (P#31)
L3 L#4 (32MB)
L2 L#32 (1024KB) + L1d L#32 (32KB) + L1i L#32 (32KB) + Core L#32 + PU L#32 (P#32)
L2 L#33 (1024KB) + L1d L#33 (32KB) + L1i L#33 (32KB) + Core L#33 + PU L#33 (P#33)
L2 L#34 (1024KB) + L1d L#34 (32KB) + L1i L#34 (32KB) + Core L#34 + PU L#34 (P#34)
L2 L#35 (1024KB) + L1d L#35 (32KB) + L1i L#35 (32KB) + Core L#35 + PU L#35 (P#35)
L2 L#36 (1024KB) + L1d L#36 (32KB) + L1i L#36 (32KB) + Core L#36 + PU L#36 (P#36)
L2 L#37 (1024KB) + L1d L#37 (32KB) + L1i L#37 (32KB) + Core L#37 + PU L#37 (P#37)
L2 L#38 (1024KB) + L1d L#38 (32KB) + L1i L#38 (32KB) + Core L#38 + PU L#38 (P#38)
L2 L#39 (1024KB) + L1d L#39 (32KB) + L1i L#39 (32KB) + Core L#39 + PU L#39 (P#39)
L3 L#5 (32MB)
L2 L#40 (1024KB) + L1d L#40 (32KB) + L1i L#40 (32KB) + Core L#40 + PU L#40 (P#40)
L2 L#41 (1024KB) + L1d L#41 (32KB) + L1i L#41 (32KB) + Core L#41 + PU L#41 (P#41)
L2 L#42 (1024KB) + L1d L#42 (32KB) + L1i L#42 (32KB) + Core L#42 + PU L#42 (P#42)
L2 L#43 (1024KB) + L1d L#43 (32KB) + L1i L#43 (32KB) + Core L#43 + PU L#43 (P#43)
L2 L#44 (1024KB) + L1d L#44 (32KB) + L1i L#44 (32KB) + Core L#44 + PU L#44 (P#44)
L2 L#45 (1024KB) + L1d L#45 (32KB) + L1i L#45 (32KB) + Core L#45 + PU L#45 (P#45)
L2 L#46 (1024KB) + L1d L#46 (32KB) + L1i L#46 (32KB) + Core L#46 + PU L#46 (P#46)
L2 L#47 (1024KB) + L1d L#47 (32KB) + L1i L#47 (32KB) + Core L#47 + PU L#47 (P#47)
L3 L#6 (32MB)
L2 L#48 (1024KB) + L1d L#48 (32KB) + L1i L#48 (32KB) + Core L#48 + PU L#48 (P#48)
L2 L#49 (1024KB) + L1d L#49 (32KB) + L1i L#49 (32KB) + Core L#49 + PU L#49 (P#49)
L2 L#50 (1024KB) + L1d L#50 (32KB) + L1i L#50 (32KB) + Core L#50 + PU L#50 (P#50)
L2 L#51 (1024KB) + L1d L#51 (32KB) + L1i L#51 (32KB) + Core L#51 + PU L#51 (P#51)
L2 L#52 (1024KB) + L1d L#52 (32KB) + L1i L#52 (32KB) + Core L#52 + PU L#52 (P#52)
L2 L#53 (1024KB) + L1d L#53 (32KB) + L1i L#53 (32KB) + Core L#53 + PU L#53 (P#53)
L2 L#54 (1024KB) + L1d L#54 (32KB) + L1i L#54 (32KB) + Core L#54 + PU L#54 (P#54)
L2 L#55 (1024KB) + L1d L#55 (32KB) + L1i L#55 (32KB) + Core L#55 + PU L#55 (P#55)
L3 L#7 (32MB)
L2 L#56 (1024KB) + L1d L#56 (32KB) + L1i L#56 (32KB) + Core L#56 + PU L#56 (P#56)
L2 L#57 (1024KB) + L1d L#57 (32KB) + L1i L#57 (32KB) + Core L#57 + PU L#57 (P#57)
L2 L#58 (1024KB) + L1d L#58 (32KB) + L1i L#58 (32KB) + Core L#58 + PU L#58 (P#58)
L2 L#59 (1024KB) + L1d L#59 (32KB) + L1i L#59 (32KB) + Core L#59 + PU L#59 (P#59)
L2 L#60 (1024KB) + L1d L#60 (32KB) + L1i L#60 (32KB) + Core L#60 + PU L#60 (P#60)
L2 L#61 (1024KB) + L1d L#61 (32KB) + L1i L#61 (32KB) + Core L#61 + PU L#61 (P#61)
L2 L#62 (1024KB) + L1d L#62 (32KB) + L1i L#62 (32KB) + Core L#62 + PU L#62 (P#62)
L2 L#63 (1024KB) + L1d L#63 (32KB) + L1i L#63 (32KB) + Core L#63 + PU L#63 (P#63)
L3 L#8 (32MB)
L2 L#64 (1024KB) + L1d L#64 (32KB) + L1i L#64 (32KB) + Core L#64 + PU L#64 (P#64)
L2 L#65 (1024KB) + L1d L#65 (32KB) + L1i L#65 (32KB) + Core L#65 + PU L#65 (P#65)
L2 L#66 (1024KB) + L1d L#66 (32KB) + L1i L#66 (32KB) + Core L#66 + PU L#66 (P#66)
L2 L#67 (1024KB) + L1d L#67 (32KB) + L1i L#67 (32KB) + Core L#67 + PU L#67 (P#67)
L2 L#68 (1024KB) + L1d L#68 (32KB) + L1i L#68 (32KB) + Core L#68 + PU L#68 (P#68)
L2 L#69 (1024KB) + L1d L#69 (32KB) + L1i L#69 (32KB) + Core L#69 + PU L#69 (P#69)
L2 L#70 (1024KB) + L1d L#70 (32KB) + L1i L#70 (32KB) + Core L#70 + PU L#70 (P#70)
L2 L#71 (1024KB) + L1d L#71 (32KB) + L1i L#71 (32KB) + Core L#71 + PU L#71 (P#71)
L3 L#9 (32MB)
L2 L#72 (1024KB) + L1d L#72 (32KB) + L1i L#72 (32KB) + Core L#72 + PU L#72 (P#72)
L2 L#73 (1024KB) + L1d L#73 (32KB) + L1i L#73 (32KB) + Core L#73 + PU L#73 (P#73)
L2 L#74 (1024KB) + L1d L#74 (32KB) + L1i L#74 (32KB) + Core L#74 + PU L#74 (P#74)
L2 L#75 (1024KB) + L1d L#75 (32KB) + L1i L#75 (32KB) + Core L#75 + PU L#75 (P#75)
L2 L#76 (1024KB) + L1d L#76 (32KB) + L1i L#76 (32KB) + Core L#76 + PU L#76 (P#76)
L2 L#77 (1024KB) + L1d L#77 (32KB) + L1i L#77 (32KB) + Core L#77 + PU L#77 (P#77)
L2 L#78 (1024KB) + L1d L#78 (32KB) + L1i L#78 (32KB) + Core L#78 + PU L#78 (P#78)
L2 L#79 (1024KB) + L1d L#79 (32KB) + L1i L#79 (32KB) + Core L#79 + PU L#79 (P#79)
L3 L#10 (32MB)
L2 L#80 (1024KB) + L1d L#80 (32KB) + L1i L#80 (32KB) + Core L#80 + PU L#80 (P#80)
L2 L#81 (1024KB) + L1d L#81 (32KB) + L1i L#81 (32KB) + Core L#81 + PU L#81 (P#81)
L2 L#82 (1024KB) + L1d L#82 (32KB) + L1i L#82 (32KB) + Core L#82 + PU L#82 (P#82)
L2 L#83 (1024KB) + L1d L#83 (32KB) + L1i L#83 (32KB) + Core L#83 + PU L#83 (P#83)
L2 L#84 (1024KB) + L1d L#84 (32KB) + L1i L#84 (32KB) + Core L#84 + PU L#84 (P#84)
L2 L#85 (1024KB) + L1d L#85 (32KB) + L1i L#85 (32KB) + Core L#85 + PU L#85 (P#85)
L2 L#86 (1024KB) + L1d L#86 (32KB) + L1i L#86 (32KB) + Core L#86 + PU L#86 (P#86)
L2 L#87 (1024KB) + L1d L#87 (32KB) + L1i L#87 (32KB) + Core L#87 + PU L#87 (P#87)
L3 L#11 (32MB)
L2 L#88 (1024KB) + L1d L#88 (32KB) + L1i L#88 (32KB) + Core L#88 + PU L#88 (P#88)
L2 L#89 (1024KB) + L1d L#89 (32KB) + L1i L#89 (32KB) + Core L#89 + PU L#89 (P#89)
L2 L#90 (1024KB) + L1d L#90 (32KB) + L1i L#90 (32KB) + Core L#90 + PU L#90 (P#90)
L2 L#91 (1024KB) + L1d L#91 (32KB) + L1i L#91 (32KB) + Core L#91 + PU L#91 (P#91)
L2 L#92 (1024KB) + L1d L#92 (32KB) + L1i L#92 (32KB) + Core L#92 + PU L#92 (P#92)
L2 L#93 (1024KB) + L1d L#93 (32KB) + L1i L#93 (32KB) + Core L#93 + PU L#93 (P#93)
L2 L#94 (1024KB) + L1d L#94 (32KB) + L1i L#94 (32KB) + Core L#94 + PU L#94 (P#94)
L2 L#95 (1024KB) + L1d L#95 (32KB) + L1i L#95 (32KB) + Core L#95 + PU L#95 (P#95)
HostBridge
PCIBridge
2 x { PCI 02:00.0-1 (SATA) }
HostBridge
PCIBridge
PCI 61:00.0 (Ethernet)
Net "ens300np0"
OpenFabrics "mlx5_0"
PCIBridge
PCIBridge
PCI 63:00.0 (VGA)
PCIBridge
2 x { PCI 65:00.0-1 (SATA) }
Package L#1
NUMANode L#1 (P#1 1134GB)
L3 L#12 (32MB)
L2 L#96 (1024KB) + L1d L#96 (32KB) + L1i L#96 (32KB) + Core L#96 + PU L#96 (P#96)
L2 L#97 (1024KB) + L1d L#97 (32KB) + L1i L#97 (32KB) + Core L#97 + PU L#97 (P#97)
L2 L#98 (1024KB) + L1d L#98 (32KB) + L1i L#98 (32KB) + Core L#98 + PU L#98 (P#98)
L2 L#99 (1024KB) + L1d L#99 (32KB) + L1i L#99 (32KB) + Core L#99 + PU L#99 (P#99)
L2 L#100 (1024KB) + L1d L#100 (32KB) + L1i L#100 (32KB) + Core L#100 + PU L#100 (P#100)
L2 L#101 (1024KB) + L1d L#101 (32KB) + L1i L#101 (32KB) + Core L#101 + PU L#101 (P#101)
L2 L#102 (1024KB) + L1d L#102 (32KB) + L1i L#102 (32KB) + Core L#102 + PU L#102 (P#102)
L2 L#103 (1024KB) + L1d L#103 (32KB) + L1i L#103 (32KB) + Core L#103 + PU L#103 (P#103)
L3 L#13 (32MB)
L2 L#104 (1024KB) + L1d L#104 (32KB) + L1i L#104 (32KB) + Core L#104 + PU L#104 (P#104)
L2 L#105 (1024KB) + L1d L#105 (32KB) + L1i L#105 (32KB) + Core L#105 + PU L#105 (P#105)
L2 L#106 (1024KB) + L1d L#106 (32KB) + L1i L#106 (32KB) + Core L#106 + PU L#106 (P#106)
L2 L#107 (1024KB) + L1d L#107 (32KB) + L1i L#107 (32KB) + Core L#107 + PU L#107 (P#107)
L2 L#108 (1024KB) + L1d L#108 (32KB) + L1i L#108 (32KB) + Core L#108 + PU L#108 (P#108)
L2 L#109 (1024KB) + L1d L#109 (32KB) + L1i L#109 (32KB) + Core L#109 + PU L#109 (P#109)
L2 L#110 (1024KB) + L1d L#110 (32KB) + L1i L#110 (32KB) + Core L#110 + PU L#110 (P#110)
L2 L#111 (1024KB) + L1d L#111 (32KB) + L1i L#111 (32KB) + Core L#111 + PU L#111 (P#111)
L3 L#14 (32MB)
L2 L#112 (1024KB) + L1d L#112 (32KB) + L1i L#112 (32KB) + Core L#112 + PU L#112 (P#112)
L2 L#113 (1024KB) + L1d L#113 (32KB) + L1i L#113 (32KB) + Core L#113 + PU L#113 (P#113)
L2 L#114 (1024KB) + L1d L#114 (32KB) + L1i L#114 (32KB) + Core L#114 + PU L#114 (P#114)
L2 L#115 (1024KB) + L1d L#115 (32KB) + L1i L#115 (32KB) + Core L#115 + PU L#115 (P#115)
L2 L#116 (1024KB) + L1d L#116 (32KB) + L1i L#116 (32KB) + Core L#116 + PU L#116 (P#116)
L2 L#117 (1024KB) + L1d L#117 (32KB) + L1i L#117 (32KB) + Core L#117 + PU L#117 (P#117)
L2 L#118 (1024KB) + L1d L#118 (32KB) + L1i L#118 (32KB) + Core L#118 + PU L#118 (P#118)
L2 L#119 (1024KB) + L1d L#119 (32KB) + L1i L#119 (32KB) + Core L#119 + PU L#119 (P#119)
L3 L#15 (32MB)
L2 L#120 (1024KB) + L1d L#120 (32KB) + L1i L#120 (32KB) + Core L#120 + PU L#120 (P#120)
L2 L#121 (1024KB) + L1d L#121 (32KB) + L1i L#121 (32KB) + Core L#121 + PU L#121 (P#121)
L2 L#122 (1024KB) + L1d L#122 (32KB) + L1i L#122 (32KB) + Core L#122 + PU L#122 (P#122)
L2 L#123 (1024KB) + L1d L#123 (32KB) + L1i L#123 (32KB) + Core L#123 + PU L#123 (P#123)
L2 L#124 (1024KB) + L1d L#124 (32KB) + L1i L#124 (32KB) + Core L#124 + PU L#124 (P#124)
L2 L#125 (1024KB) + L1d L#125 (32KB) + L1i L#125 (32KB) + Core L#125 + PU L#125 (P#125)
L2 L#126 (1024KB) + L1d L#126 (32KB) + L1i L#126 (32KB) + Core L#126 + PU L#126 (P#126)
L2 L#127 (1024KB) + L1d L#127 (32KB) + L1i L#127 (32KB) + Core L#127 + PU L#127 (P#127)
L3 L#16 (32MB)
L2 L#128 (1024KB) + L1d L#128 (32KB) + L1i L#128 (32KB) + Core L#128 + PU L#128 (P#128)
L2 L#129 (1024KB) + L1d L#129 (32KB) + L1i L#129 (32KB) + Core L#129 + PU L#129 (P#129)
L2 L#130 (1024KB) + L1d L#130 (32KB) + L1i L#130 (32KB) + Core L#130 + PU L#130 (P#130)
L2 L#131 (1024KB) + L1d L#131 (32KB) + L1i L#131 (32KB) + Core L#131 + PU L#131 (P#131)
L2 L#132 (1024KB) + L1d L#132 (32KB) + L1i L#132 (32KB) + Core L#132 + PU L#132 (P#132)
L2 L#133 (1024KB) + L1d L#133 (32KB) + L1i L#133 (32KB) + Core L#133 + PU L#133 (P#133)
L2 L#134 (1024KB) + L1d L#134 (32KB) + L1i L#134 (32KB) + Core L#134 + PU L#134 (P#134)
L2 L#135 (1024KB) + L1d L#135 (32KB) + L1i L#135 (32KB) + Core L#135 + PU L#135 (P#135)
L3 L#17 (32MB)
L2 L#136 (1024KB) + L1d L#136 (32KB) + L1i L#136 (32KB) + Core L#136 + PU L#136 (P#136)
L2 L#137 (1024KB) + L1d L#137 (32KB) + L1i L#137 (32KB) + Core L#137 + PU L#137 (P#137)
L2 L#138 (1024KB) + L1d L#138 (32KB) + L1i L#138 (32KB) + Core L#138 + PU L#138 (P#138)
L2 L#139 (1024KB) + L1d L#139 (32KB) + L1i L#139 (32KB) + Core L#139 + PU L#139 (P#139)
L2 L#140 (1024KB) + L1d L#140 (32KB) + L1i L#140 (32KB) + Core L#140 + PU L#140 (P#140)
L2 L#141 (1024KB) + L1d L#141 (32KB) + L1i L#141 (32KB) + Core L#141 + PU L#141 (P#141)
L2 L#142 (1024KB) + L1d L#142 (32KB) + L1i L#142 (32KB) + Core L#142 + PU L#142 (P#142)
L2 L#143 (1024KB) + L1d L#143 (32KB) + L1i L#143 (32KB) + Core L#143 + PU L#143 (P#143)
L3 L#18 (32MB)
L2 L#144 (1024KB) + L1d L#144 (32KB) + L1i L#144 (32KB) + Core L#144 + PU L#144 (P#144)
L2 L#145 (1024KB) + L1d L#145 (32KB) + L1i L#145 (32KB) + Core L#145 + PU L#145 (P#145)
L2 L#146 (1024KB) + L1d L#146 (32KB) + L1i L#146 (32KB) + Core L#146 + PU L#146 (P#146)
L2 L#147 (1024KB) + L1d L#147 (32KB) + L1i L#147 (32KB) + Core L#147 + PU L#147 (P#147)
L2 L#148 (1024KB) + L1d L#148 (32KB) + L1i L#148 (32KB) + Core L#148 + PU L#148 (P#148)
L2 L#149 (1024KB) + L1d L#149 (32KB) + L1i L#149 (32KB) + Core L#149 + PU L#149 (P#149)
L2 L#150 (1024KB) + L1d L#150 (32KB) + L1i L#150 (32KB) + Core L#150 + PU L#150 (P#150)
L2 L#151 (1024KB) + L1d L#151 (32KB) + L1i L#151 (32KB) + Core L#151 + PU L#151 (P#151)
L3 L#19 (32MB)
L2 L#152 (1024KB) + L1d L#152 (32KB) + L1i L#152 (32KB) + Core L#152 + PU L#152 (P#152)
L2 L#153 (1024KB) + L1d L#153 (32KB) + L1i L#153 (32KB) + Core L#153 + PU L#153 (P#153)
L2 L#154 (1024KB) + L1d L#154 (32KB) + L1i L#154 (32KB) + Core L#154 + PU L#154 (P#154)
L2 L#155 (1024KB) + L1d L#155 (32KB) + L1i L#155 (32KB) + Core L#155 + PU L#155 (P#155)
L2 L#156 (1024KB) + L1d L#156 (32KB) + L1i L#156 (32KB) + Core L#156 + PU L#156 (P#156)
L2 L#157 (1024KB) + L1d L#157 (32KB) + L1i L#157 (32KB) + Core L#157 + PU L#157 (P#157)
L2 L#158 (1024KB) + L1d L#158 (32KB) + L1i L#158 (32KB) + Core L#158 + PU L#158 (P#158)
L2 L#159 (1024KB) + L1d L#159 (32KB) + L1i L#159 (32KB) + Core L#159 + PU L#159 (P#159)
L3 L#20 (32MB)
L2 L#160 (1024KB) + L1d L#160 (32KB) + L1i L#160 (32KB) + Core L#160 + PU L#160 (P#160)
L2 L#161 (1024KB) + L1d L#161 (32KB) + L1i L#161 (32KB) + Core L#161 + PU L#161 (P#161)
L2 L#162 (1024KB) + L1d L#162 (32KB) + L1i L#162 (32KB) + Core L#162 + PU L#162 (P#162)
L2 L#163 (1024KB) + L1d L#163 (32KB) + L1i L#163 (32KB) + Core L#163 + PU L#163 (P#163)
L2 L#164 (1024KB) + L1d L#164 (32KB) + L1i L#164 (32KB) + Core L#164 + PU L#164 (P#164)
L2 L#165 (1024KB) + L1d L#165 (32KB) + L1i L#165 (32KB) + Core L#165 + PU L#165 (P#165)
L2 L#166 (1024KB) + L1d L#166 (32KB) + L1i L#166 (32KB) + Core L#166 + PU L#166 (P#166)
L2 L#167 (1024KB) + L1d L#167 (32KB) + L1i L#167 (32KB) + Core L#167 + PU L#167 (P#167)
L3 L#21 (32MB)
L2 L#168 (1024KB) + L1d L#168 (32KB) + L1i L#168 (32KB) + Core L#168 + PU L#168 (P#168)
L2 L#169 (1024KB) + L1d L#169 (32KB) + L1i L#169 (32KB) + Core L#169 + PU L#169 (P#169)
L2 L#170 (1024KB) + L1d L#170 (32KB) + L1i L#170 (32KB) + Core L#170 + PU L#170 (P#170)
L2 L#171 (1024KB) + L1d L#171 (32KB) + L1i L#171 (32KB) + Core L#171 + PU L#171 (P#171)
L2 L#172 (1024KB) + L1d L#172 (32KB) + L1i L#172 (32KB) + Core L#172 + PU L#172 (P#172)
L2 L#173 (1024KB) + L1d L#173 (32KB) + L1i L#173 (32KB) + Core L#173 + PU L#173 (P#173)
L2 L#174 (1024KB) + L1d L#174 (32KB) + L1i L#174 (32KB) + Core L#174 + PU L#174 (P#174)
L2 L#175 (1024KB) + L1d L#175 (32KB) + L1i L#175 (32KB) + Core L#175 + PU L#175 (P#175)
L3 L#22 (32MB)
L2 L#176 (1024KB) + L1d L#176 (32KB) + L1i L#176 (32KB) + Core L#176 + PU L#176 (P#176)
L2 L#177 (1024KB) + L1d L#177 (32KB) + L1i L#177 (32KB) + Core L#177 + PU L#177 (P#177)
L2 L#178 (1024KB) + L1d L#178 (32KB) + L1i L#178 (32KB) + Core L#178 + PU L#178 (P#178)
L2 L#179 (1024KB) + L1d L#179 (32KB) + L1i L#179 (32KB) + Core L#179 + PU L#179 (P#179)
L2 L#180 (1024KB) + L1d L#180 (32KB) + L1i L#180 (32KB) + Core L#180 + PU L#180 (P#180)
L2 L#181 (1024KB) + L1d L#181 (32KB) + L1i L#181 (32KB) + Core L#181 + PU L#181 (P#181)
L2 L#182 (1024KB) + L1d L#182 (32KB) + L1i L#182 (32KB) + Core L#182 + PU L#182 (P#182)
L2 L#183 (1024KB) + L1d L#183 (32KB) + L1i L#183 (32KB) + Core L#183 + PU L#183 (P#183)
L3 L#23 (32MB)
L2 L#184 (1024KB) + L1d L#184 (32KB) + L1i L#184 (32KB) + Core L#184 + PU L#184 (P#184)
L2 L#185 (1024KB) + L1d L#185 (32KB) + L1i L#185 (32KB) + Core L#185 + PU L#185 (P#185)
L2 L#186 (1024KB) + L1d L#186 (32KB) + L1i L#186 (32KB) + Core L#186 + PU L#186 (P#186)
L2 L#187 (1024KB) + L1d L#187 (32KB) + L1i L#187 (32KB) + Core L#187 + PU L#187 (P#187)
L2 L#188 (1024KB) + L1d L#188 (32KB) + L1i L#188 (32KB) + Core L#188 + PU L#188 (P#188)
L2 L#189 (1024KB) + L1d L#189 (32KB) + L1i L#189 (32KB) + Core L#189 + PU L#189 (P#189)
L2 L#190 (1024KB) + L1d L#190 (32KB) + L1i L#190 (32KB) + Core L#190 + PU L#190 (P#190)
L2 L#191 (1024KB) + L1d L#191 (32KB) + L1i L#191 (32KB) + Core L#191 + PU L#191 (P#191)
HostBridge
PCIBridge
2 x { PCI 82:00.0-1 (SATA) }
HostBridge
PCIBridge
PCI a1:00.0 (Ethernet)
Net "ens340np0"
OpenFabrics "mlx5_1"
HostBridge
PCIBridge
2 x { PCI e2:00.0-1 (SATA) }
Block(Disk) "sda"