disk-compilebench
2 x Intel Xeon Platinum 8163 testing with a Alibaba Cloud ECS (A9.32 BIOS) and ASPEED Family on CentOS 7.6.1810 via the Phoronix Test Suite.
2 x Intel Xeon Platinum 8163 - ASPEED Family -
Processor: 2 x Intel Xeon Platinum 8163 @ 2.50GHz (48 Cores / 96 Threads), Motherboard: Alibaba Cloud ECS (A9.32 BIOS), Chipset: Intel Sky Lake-E DMI3 Registers, Memory: 12 x 16384 MB DDR4-2666MT/s Hynix HMA82GR7AFR4N-VK, Disk: 50GB, Graphics: ASPEED Family, Network: Red Hat Virtio device
OS: CentOS 7.6.1810, Kernel: 3.10.0-957.5.1.el7.x86_64 (x86_64), Compiler: GCC 4.8.5 20150623, File-System: ext4
Disk Notes: NONE / data=ordered,relatime,rw
Processor Notes: Scaling Governor: acpi-cpufreq conservative
Python Notes: Python 2.7.5
Security Notes: KPTI + Load fences __user pointer sanitization + Retpoline on Skylake+ + SSB disabled via prctl and seccomp + PTE Inversion; VMX: SMT vulnerable L1D conditional cache flushes
Compile Bench
Compilebench tries to age a filesystem by simulating some of the disk IO common in creating, compiling, patching, stating and reading kernel trees. It indirectly measures how well filesystems can maintain directory locality as the disk fills up and directories age. This current test is setup to use the makej mode with 10 initial directories Learn more via the OpenBenchmarking.org test page.
2 x Intel Xeon Platinum 8163 - ASPEED Family -
Processor: 2 x Intel Xeon Platinum 8163 @ 2.50GHz (48 Cores / 96 Threads), Motherboard: Alibaba Cloud ECS (A9.32 BIOS), Chipset: Intel Sky Lake-E DMI3 Registers, Memory: 12 x 16384 MB DDR4-2666MT/s Hynix HMA82GR7AFR4N-VK, Disk: 50GB, Graphics: ASPEED Family, Network: Red Hat Virtio device
OS: CentOS 7.6.1810, Kernel: 3.10.0-957.5.1.el7.x86_64 (x86_64), Compiler: GCC 4.8.5 20150623, File-System: ext4
Disk Notes: NONE / data=ordered,relatime,rw
Processor Notes: Scaling Governor: acpi-cpufreq conservative
Python Notes: Python 2.7.5
Security Notes: KPTI + Load fences __user pointer sanitization + Retpoline on Skylake+ + SSB disabled via prctl and seccomp + PTE Inversion; VMX: SMT vulnerable L1D conditional cache flushes
Testing initiated at 8 May 2019 21:44 by user root.