RPI-Cachebench
Cachebench
Cachbet on the PI REV 2B
Processor: ARMv6-compatible rev 7 @ 0.70GHz (1 Core), Motherboard: BCM2708, Memory: 437MB, Disk: 8GB SD08G
OS: Debian Linux 7.5, Kernel: 3.12.22+ (armv6l), Desktop: LXDE 0.5.10, Display Server: X Server 1.12.4, Compiler: GCC 4.6.3, File-System: ext4, Screen Resolution: 1920x1200
Compiler Notes: --build=arm-linux-gnueabihf --disable-sjlj-exceptions --enable-checking=release --enable-clocale=gnu --enable-gnu-unique-object --enable-languages=c,c++,fortran,objc,obj-c++ --enable-libstdcxx-debug --enable-libstdcxx-time=yes --enable-nls --enable-objc-gc --enable-plugin --enable-shared --enable-threads=posix --host=arm-linux-gnueabihf --target=arm-linux-gnueabihf --with-arch=armv6 --with-float=hard --with-fpu=vfp -v
Processor Notes: Scaling Governor: BCM2835 Freq powersave
CacheBench
This is a performance test of CacheBench, which is part of LLCbench. CacheBench is designed to test the memory and cache bandwidth performance Learn more via the OpenBenchmarking.org test page.
Cachbet on the PI REV 2B
Processor: ARMv6-compatible rev 7 @ 0.70GHz (1 Core), Motherboard: BCM2708, Memory: 437MB, Disk: 8GB SD08G
OS: Debian Linux 7.5, Kernel: 3.12.22+ (armv6l), Desktop: LXDE 0.5.10, Display Server: X Server 1.12.4, Compiler: GCC 4.6.3, File-System: ext4, Screen Resolution: 1920x1200
Compiler Notes: --build=arm-linux-gnueabihf --disable-sjlj-exceptions --enable-checking=release --enable-clocale=gnu --enable-gnu-unique-object --enable-languages=c,c++,fortran,objc,obj-c++ --enable-libstdcxx-debug --enable-libstdcxx-time=yes --enable-nls --enable-objc-gc --enable-plugin --enable-shared --enable-threads=posix --host=arm-linux-gnueabihf --target=arm-linux-gnueabihf --with-arch=armv6 --with-float=hard --with-fpu=vfp -v
Processor Notes: Scaling Governor: BCM2835 Freq powersave
Testing initiated at 25 June 2014 09:26 by user root.